Improving Cache Energy Efficiency for Green Computing

Green computing refers to the study and practice of designing, operating and disposing computing systems effectively in a manner which creates minimal or no impact on the environment. With increasing use of computing systems, their total energy consumption has also increased and it has been estimated that the carbon emission of ICT (information and communication technology) will triple from 2002 to 2020 (Smarr, 2010). Hence, techniques for improving the energy-efficiency of computing systems are extremely important to achieve the goals of green-computing and sustainability. In nearly all the computer systems, power consumption presents itself as a primary design constraint. For example, in mobile and embedded computing systems, the amount of power consumed directly affects the battery lifetime. In desktop systems, excessive power dissipation has been one of the important reasons for the halt of clock frequency increases. To alleviate the problem of power dissipation, chip multiprocessors (CMPs) have been adopted since they allow high-performance computing within cost-effective power and thermal envelopes. In Internet datacenters and supercomputers, power consumption has been on rise. For example, each of the 10 most powerful supercomputers on the TOP500 List require up to 10 megawatts of peak power (Feng et al., 2007). This amount of power is sufficient to sustain a city of 40,000. The issue of power consumption drives major design decisions in modern companies and the increased power levels puts stress on the power transmission systems. Thus, high power consumption has significant socio-economic impacts. Among different on-chip components, caches contribute a major fraction of chip-power consumption (Lahiri et al., 2004). In several processor chips, caches occupy more than 50% of the total area. Further, their size is increasing to fulfill the demands of performance-critical applications (Pande et al., 2009, Mittal et al., 2008, Khaitan et al., 2012). Also, the number of cores on a single chip is increasing; for example, IBM’s POWER7, Intel’s E7-8800 Series and AMD’s Opteron 6000 Series processors use 8 to 16 cores on a single chip. To feed the large number of cores and to bridge the widening gap between the speed of processor core and DRAM memory, large sized caches are being used; as an example, Intel’s E7-8800 processor uses 24MB L3 cache. Further, with each CMOS technology generation, leakage power has been dramatically increasing (Rodriguez et al. 2006). Hence, managing power consumption of caches is becoming a crucial issue in modern processor design (Mittal, 2014). In this chapter, we discuss the principles and techniques used for saving cache leakage energy. We also discuss the example of commercial chips which provide hardware functionality for saving cache energy.